“Macros” or “cores” are functional circuit elements or building blocks or units of logic that can be used by chip fabricators to create an application specific integrated circuit (ASIC) or a field programmable gate array (FPGA). Two common types of macros are referred to as “soft” and “hard” macros. Soft macros include logic for performing a particular function along with various interconnection rules for connecting sub-portions of the soft macro and/or for connecting portions of the soft macro to other elements outside the soft macro. They may comprise, for example, a gate-level netlist. Soft macros do not specify a physical wiring pattern and thus allow for flexibility in final physical implementation, however, due to the lack of a pre-specified physical wiring pattern, they may need to be optimized for desired performance and/or final layout in a floor-plan. Hard macros specify a fixed wiring pattern and are not modifiable. Hard macros are thus less flexible than soft macros but can be optimized for performance and physical layout prior to use.
Hard and soft macros are used in two dimensional integrated circuits. However, it is becoming more common to stack multiple integrated circuit layers and form three dimensional integrated circuits or “3D IC's” to achieve higher device packing density, lower interconnect RC delay, and lower cost. The size and configuration of macros must be taken into account during the floor-planning of a chip, especially a 3D IC. Soft macros may be modified to a degree and thus it may sometimes be possible to allow connections from elements in a layer above the soft macro to elements in a layer below the soft macro to run through the soft macro. Hard macros, however, have a fixed form factor, and it is generally necessary to route inter-layer connections around them. This increases the length of various interconnections and may require the use of additional buffers to compensate. Regions near the edges of hard macros can also become congested with conduction pathways from elements above or below the hard macro that need to pass by the hard macro to reach another layer of the chip.
FIG. 1 shows a multi-layer chip 100 having a first layer 102 having a first circuit element 104, a second layer 106 having a hard macro 108, and a third layer 110 having a second circuit element 112. The first circuit element 104 and/or second circuit element 112 could alternately represent pins or connection pads for the multi-layer chip 100 rather than actual circuit elements. The design of the chip 100 requires that the first circuit element 104 be connected to the second circuit element 112 located on the layer beneath the hard macro and two layers below the first circuit element 104. In order to make this connection, a via 114 is provided at a distance from the hard macro 108, and the first circuit element 104 is connected to the via 114 by a first trace 116 and the second circuit element is connected to the via 114 by a second trace 118. If the hard macro 108 were not present, a via could be provided directly beneath or closer to the first circuit element 104 or the second circuit element 112 to shorten the connection path therebetween. The presence of the hard macro 108 in the second layer 106 between the first and second circuit elements 104, 112 increases the length of the connection between the first and second circuit elements 104, 112.
In some cases it may be possible to break a single large hard macro into two or more smaller hard macros and provide the necessary interconnection rules for allowing the hard macros to communicate and to operate as if they were a single hard macro. This arrangement, however, requires on-chip optimization and may lead to a decrease in chip performance. It would therefore be desirable to provide a hard macro that retains the benefits of hard macros discussed above and which allows for greater flexibility in routing.